1 特性

1.1 通用特性

• 电源范围：2.4V ~ 3.6V
• 最高IO口电压：5V
• ADC/DAC精度：24bit
• 控制总线：L3/I2C, 都有两个地址可选
  
• ADC采样率范围：8~55kHz
• DAC采样率范围：8~100kHz
• 电源管理单元
  • 独立电源管理ADC/AVC/DAC/PLL/耳机驱动
  • ADC/PGA等模电模组可以独立关闭其电源
  • 当DAC/ADC电源关闭时，它们使用的时钟也会一起关闭来节省电源
  • 默认情况下，IC上电后，整个芯片都处于电源关闭状态
• ADC和DAC可以运行在不同的时钟频率下，不然选择系统时钟(SYSCLK)，不然选择WSPLL
• ADC和PGA都集成了高通滤波器来去除直流偏置
• 抽取滤波器配备了数字自动增益控制模块
• 单声道麦克风输入配备了29dB固定增益的低噪声放大器(LNA)和0~30dB可变增益控制(2dB步进)
• DAC集成了数字滤波器
• 有单独的单端线路输出和立体声耳机输出，均可驱动16Ω的负载。耳机输出内置了短路保护，并且可以通过L3/I2C来读取短路状态
• 插值器中集成了数字静音检测，可通过L3/I2C来从读取播放时的静音状态

1.2 多格式输入

• 从机BCK、WS信号输入
• I2S总线格式
• MSB对齐格式兼容
• LSB对齐格式兼容

1.3 多格式输出

• 数字输出可选：
  • 抽取器ADC信号输出
  • 插值器DSP中的数字混音器输出

1.4 ADC前置特性

• ADC配合抽取器可以使用系统时钟(SYSCLK)，也可以使用从WSI生成的WSPLL时钟
• 立体声线路输入可配备PGA来获取0 ~ 24dB的增益(3dB步进)
• 麦克风单声道输入可配备LNA/VGA来获取29dB的固定增益0 ~ 30dB可变增益控制
• 左右声道可独立控制音量和静音，控制范围从+24dB ~ -63.5dB，0.5dB步进

1.5 DAC特性

• DAC配合插值器可以使用系统时钟(SYSCLK)，也可以使用从WSI生成的WSPLL时钟
• 左右声道可通过L3/I2C进行独立的对数音量控制，控制范围从+0dB ~ -78dB，0.25dB步进
• 数字化频段调整，重低音、高音可通过L3/I2C调节
• 数字化去加重采样频率支持：32, 44.1, 48, 96kHz
• cos曲线包络静音
• 输出信号极性可控
• 相同采样率下，ADC可和I2S输入信号一起混音输出

2 功能描述

2.1 时钟模式

UDA1380支持使用I2S总线上主机提供的SYSCLK(或叫MCLK)，也支持由WS分频产生的内部时钟作为MCLK(WSPLL模式)。

• 使用SYSCLK时，可以用跳线指定SYSCLK使用TX_MCLK还是RX_MCLK，同时也需要指定输入的SYSCLK时钟频率是采样频率的256倍、384倍、512倍还是768倍(详见I2S协议对MCLK的定义)
• 使用WSPLL时，只能使用WSI信号作为内部时钟的分频源，同时需要指定WSI信号的频率范围是在6.25 ~ 12.5kHz、
  12.5 ~ 25kHz、25 ~ 50kHz还是50 ~ 100kHz。

UDA1380有几种时钟模式可以使用:

• ADC和DAC都同时运行在SYSCLK下，此时WSPLL就应该处于断电模式
• ADC和DAC都同时运行在WSPLL下，那么需要WSI输入的信号来分频产生内部时钟
• ADC可使用SYSCLK信号，而DAC可使用与SYSCLK频率不同的WSI产生的内部时钟信号

如果只使用UDA1380的模拟ADC输入功能和I2S数字信号输出，而没有I2S数字信号输入，则没有WSI信号可用，是否会有问题？(待朕后续求证~=￣ω￣=)

2.1.1 WSPLL使用

2.1.2 时钟分布

2.2 ADC前置模拟信号

2.2.1 应用模式和断电模式

2.3 ADC抽取滤波器

2.3.1 负载检测

2.3.2 音量控制

2.3.3 静音

2.3.4 自动增益控制

2.4 DAC插值滤波器

2.4.1 数字静音

2.4.2 声音特性

2.5 噪声整形器

2.6 滤波流数模转换器(FSDAC)

2.6.1 介绍

2.6.2 模拟混音器输入

2.7 耳机驱动

2.8 混音器

2.8.1 数字混音器

2.8.2 模拟混音器

2.9 应用模式

2.10 带电重置

2.11 断电模式

2.11.1 模拟前置输入

2.11.2 FSDAC电源控制

2.12 啪嗒声的抑制

2.13 数字音频数据输入输出

2.13.1 数字音频输入接口

2.13.2 数字音频输出接口

2.14 数字音频输入接口

3 I2C接口描述

UDA1380即能支持I2C接口也能L3接口，I2C和L3接口都是通过相同的寄存器来控制模块的特性。
单片机和UDA1380之间的数据交换和控制信息都通过下面几个针脚来完成：

• SCL，I2C时钟脚
• SDA，I2C数据脚

3.1 寻址

UDA1380的I2C地址为0X30(A1位为0)或0x34(A1位为1)。和大多数I2C设备一样，写数据时，需要对地址+1，即：

• 读数据时，地址为0x30或0x34
• 写数据时，地址为0x31或0x35

3.2 寄存器

寄存器 读写模式 功能 0x00 读写 评估模式、WSPLL配置、时钟分频配置、时钟选择配置 0x01 读写 I2S总线IO配置 0x02 读写 电源控制 0x03 读写 模拟混音器 0x04 读写 预留 0x10 读写 主音量控制 0x11 读写 混音器音量控制 0x12 读写 模式选择、左右声道重低音调节、左右声道高音调节 0x13 读写 主静音、左右声道去加重、左右声道静音 0x14 读写 混音器、静音探测、插值滤波器超采样配置 0x18 只读 插值滤波器状态 0x20 读写 抽取器音量控制 0x21 读写 可编程增益放大器配置和静音 0x22 读写 ADC配置 0x23 读写 自动增益控制 0x28 只读 抽取器状态 0x7F 读写 恢复L3默认值

3.2.1 [0x00] 评估模式、WSPLL配置、时钟分频配置、时钟选择配置

#define TRUE 1 #define FALSE 0 #define SYSCLK 0 #define WSPLL 1 #define SYS_DIV_256FS 0 #define SYS_DIV_384FS 1 #define SYS_DIV_512FS 2 #define SYS_DIV_768FS 3 #define PLL_6.25_12.5 0 #define PLL_12.5_25 1 #define PLL_25_50 2 #define PLL_50_100 3 struct { uint8 evaluationMode : 3; // [15:13], default = 0 uint8 reserved0 : 1; // [12], default = 0 uint8 adcClockEnabled : 1; // [11], default = TRUE uint8 decimatorClockEnabled : 1; // [10], default = FALSE uint8 fsdacClockEnabled : 1; // [9], default = TRUE uint8 interpolatorClockEnabled : 1; // [8], default = TRUE uint8 reserved1 : 2; // [7:6], default = 0 uint8 adcClockSelect : 1; // [5], default = SYSCLK uint8 dacClockSelect : 1; // [4], default = SYSCLK uint8 systemClockInputDividers : 2; // [3:2], default = SYS_DIV_256FS, input clock on pin SYSCLK uint8 pllSetting : 2; // [1:0], default = PLL_25_50, input frequency range(kHz) on pin WSI };

• ADC为模拟输入的转为数字信号的转换器，在UDA1380中信号是以数字信号形式来处理的，所以要输入模拟音频信号时(Line in或Mic)都需要启用ADC
• Decimator这里准确的说应该是抽取滤波器，因为数字信号在ADC里是以不断采样模拟信号得来的，所以采样后会对信号做一定的滤波来优化信号的质量。所以启用ADC时，伴随就要启用DecimatorFilter了
• FSDAC为UDA1380使用的DAC，全称为流滤波数模转换器(Filter Stream DAC)。它从噪声整形器接受字节流来转换为模拟音频信号输出
• Interpolator这里指的是插值滤波器，离散的数字信号转换为连续的模拟音频信号时，会通过插值滤波器的处理，提高输出的模拟信号的质量。所以启用DAC来输出模拟信号时，伴随需要启用InterpolatorFilter来优化数模转换
• ADC和DAC可以选择SYSCLK和WSPLL两种时钟，但因为SYSCLK需要的MCLK是高频时钟，对布线要求高，容易产生干扰，所以很多方案都放弃了MCLK。所以建议采用WSPLL来通过WS信号生成内部所需的时钟

3.2.2 [0x01] I2S总线IO配置

#define INPUT_I2S 0 #define INPUT_LSB_16BITS 1 #define INPUT_LSB_18BITS 2 #define INPUT_LSB_20BITS 3 #define INPUT_MSB 4 #define OUTPUT_I2S 0 #define OUTPUT_LSB_16BITS 0 #define OUTPUT_LSB_18BIS 0 #define OUTPUT_LSB_20BITS 0 #define OUTPUT_LSB_24BITS 0 #define OUTPUT_MSB 0 #define DECIMATOR 0 #define DIGITAL_MIXER 1 #define SLAVE 0 #define MASTER 1 struct { uint8 reserved0 : 5; // [15:11], default = 0 uint8 digitalDataInputFormat : 2; // [10:8], default = INPUT_I2S uint8 reserved1 : 1; // [7], default = 0 uint8 digitalOutputInterfaceSource : 1; // [6], default = DECIMATOR uint8 reserved2 : 1; // [5], default = 0 uint8 digitalOutputInterfaceMode : 1; // [4], default = SLAVE uint8 reserved3 : 1; // [3], default = 0 uint8 digitalDataOutputFormat : 3; // [2:0], default = OUTPUT_I2S };

3.2.3 [0x02] 电源控制

#define TRUE 1 #define FALSE 0 #define POWER_OFF 0 #define POWER_ON 1 struct { uint8 pllPower : 1; // [15], default = POWER_OFF uint8 reserved0 : 1; // [14], default = 0 uint8 headphonePower : 1; // [13], default = POWER_OFF uint8 reserved1 : 2; // [12:11], default = 0 uint8 dacPower : 1; // [10], default = POWER_OFF uint8 reserved2 : 1; // [9], default = 0 uint8 biasPower : 1; // [8], default = POWER_OFF uint8 avcEnabled : 1; // [7], default = FALSE, enable the analog mixer uint8 avcPower : 1; // [6], default = POWER_OFF uint8 reserved3 : 1; // [5], default = 0 uint8 lnaPower : 1; // [4], default = POWER_OFF uint8 pgaLeftPower : 1; // [3], default = POWER_OFF, left channel PGA power uint8 adcLeftPower : 1; // [2], default = POWER_OFF, left channel ADC power uint8 pgarRightPower : 1; // [1], default = POWER_OFF, right channel PGA power uint8 adcRightPower : 1; // [0], default = POWER_OFF, right channel PGA power };

3.2.4 [0x03] 模拟混音器

#define AVC_MUTE 0x3F #define AVC_MAX_VOLUME 0 #define AVC_MIN_VOLUME 44 struct { uint8 reserved0 : 2; // [15:14], default = 0 uint8 analogVolumeLeft : 6; // [13:8], default = AVC_MUTE, range is [0, 44] mapping to [16.5dB, -∞dB], step is 0.5dB uint8 reserved1 : 2; // [7:6], default = 0 uint8 analogVolumeRight : 6; // [5:0], default = AVC_MUTE, range is [0, 44] mapping to [16.5dB, -∞dB], step is 0.5dB };

3.2.5 [0x04] 预留

#define RESREVED 0x2 struct { uint8 reserved0 : 5; // [15:11], default = 0 uint8 RSV0 : 3; // [10:8], default = RESREVED uint8 reserved1 : 5; // [7:3], default = 0 uint8 RSV1 : 3; // [2:0], default = RESREVED };

3.2.6 [0x10] 主音量控制

#define MASTER_MUTE 0xFC #define MASTER_MAX_VOLUME 0 #define MASTER_MIN_VOLUME 252 struct { uint8 masterVolumeRight : 8; // [15:8], default = MASTER_MAX_VOLUME, range is [0, 252] mapping to [0dB, -78dB], step is 0.25dB uint8 masterVolumeLeft : 8; // [7:0], default = MASTER_MAX_VOLUME, range is [0, 252] mapping to [0dB, -78dB], step is 0.25dB };

3.2.7 [0x11] 混音器音量控制

#define MIXER_MUTE 0xFC #define MIXER_MAX_VOLUME 0 #define MIXER_MIN_VOLUME 228 struct { uint8 digitalMixerVolume2 : 8; // [15:8], default = MIXER_MAX_VOLUME, range is [0, 228] mapping to [0dB, -72dB], step is 0.25dB uint8 digitalMixerVolume1 : 8; // [7:0], default = MIXER_MUTE, range is [0, 228] mapping to [0dB, -72dB], step is 0.25dB };

3.2.8 [0x12] 模式选择、左右声道重低音调节、左右声道高音调节

#define TONE_LEVEL_FLAT 0 #define TONE_LEVEL_MIN 1 #define TONE_LEVEL_MID 2 #define TONE_LEVEL_MAX 3 #define TONE_TREBLE_MIN 0 #define TONE_TREBLE_MAX 3 #define TONE_BASS_BOOST_MIN 0 #define TONE_BASS_BOOST_MAX 15 struct { uint8 toneLevel : 2; // [15:14], default = TONE_LEVEL_FLAT uint8 trebleLeft : 2; // [13:12], default = TONE_TREBLE_MIN uint8 bassBoostLeft : 4; // [11:8], default = TONE_BBE_MIN uint8 reserved : 2; // [7:6], default = 0 uint8 trebleRight : 2; // [5:4], default = TONE_TREBLE_MIN uint8 bassBoostRight : 4; // [3:0], default = TONE_BBE_MIN };

3.2.9 [0x13] 主静音、左右声道去加重、左右声道静音

#define SOFTWARE_UNMUTE 0 #define SOFTWARE_MUTE 1 #define DEEMPHASIS_OFF 0 #define DEEMPHASIS_32KHZ 1 #define DEEMPHASIS_44.1KHZ 2 #define DEEMPHASIS_48KHZ 3 #define DEEMPHASIS_96KHZ 4 struct { uint8 reserved0 : 1; // [15], default = 0 uint8 masterMute : 1; // [14], default = SOFTWARE_MUTE uint8 reserved1 : 2; // [13:12], default = 0 uint8 channel2Mute : 1; // [11], default = SOFTWARE_MUTE uint8 channel2Deemphasis : 3; // [10:8], default = 0 uint8 reserved2 : 3; // [7:4], default = 0 uint8 channel1Mute : 1; // [3], default = SOFTWARE_UNMUTE uint8 channel1Deemphasis : 3; // [2:0], default = 0 };

3.2.10 [0x14] 混音器、静音探测、插值滤波器超采样配置

#define DAC_OUTPUT_NORMAL 0 #define DAC_OUTPUT_INVERT 1 #define ORDER_3RD_SHAPER 0 #define ORDER_5RD_SHAPER 1 #define MIXING_OFF 0 #define MIXING_CHANNEL1_SOLO 1 #define MIXING_BEFORE_PROCESS 2 #define MIXING_AFTER_PROCESS 3 #define NO_OVERRULING 0 #define OVERRULING 1 #define SILENCE_DETECT_DISABLE 0 #define SILENCE_DETECT_ENABLE 1 #define SILENCE_DETECT_3200_SAMPLES 0 #define SILENCE_DETECT_4800_SAMPLES 1 #define SILENCE_DETECT_9600_SAMPLES 2 #define SILENCE_DETECT_19200_SAMPLES 3 #define OVERSAMPLING_1X 0 #define OVERSAMPLING_2X 1 #define OVERSAMPLING_4X 2 struct { uint8 dacPolarity : 1; // [15], default = DAC_OUTPUT_NORMAL uint8 noiseShaperOrder : 1; // [14], default = ORDER_3RD_SHAPER uint8 mixerSignalControl : 2; // [13:12], default = MIXING_OFF uint8 reserved0 : 4; // [11:8], default = 0 uint8 silenceDetector : 1; // [7], default = NO_OVERRULING uint8 silenceDetectorEnabled : 1; // [6], default = SILENCE_DETECT_DISABLE uint8 silenceDetectorSetting : 2; // [5:4], default = SILENCE_DETECT_3200_SAMPLES uint8 reserved1 : 2; // [3:2], default = 0 uint8 oversampling : 2; // [1:0], default = OVERSAMPLING_1X };

3.2.11 [0x18] 插值滤波器状态

3.2.12 [0x20] 抽取器音量控制

#define ADC_GAIN_MAX 48 #define ADC_GAIN_NONE 0 #define ADC_GAIN_MIN -127 struct { int8 adcVolumeLeft : 8; // [15:8], default = ADC_GAIN_NONE, range is [-127, 48] mapping to [-∞dB, 24dB], step is 0.5dB int8 adcVolumeRight : 8; // [7:0], default = ADC_GAIN_NONE, range is [-127, 48] mapping to [-∞dB, 24dB], step is 0.5dB };

3.2.13 [0x21] 可编程增益放大器配置和静音

#define DECIMATOR_UNMUTE 0 #define DECIMATOR_MUTE 1 #define ADC_INPUT_AMPLIFIER_GAIN_MIN 0 #define ADC_INPUT_AMPLIFIER_GAIN_MAX 8 struct { uint8 decimatorMute : 1; // [15], default = DECIMATOR_MUTE uint8 reserved0 : 3; // [14:12], default = 0 uint8 adcInputAmplifierGainRight : 4; // [11:8], default = ADC_INPUT_AMPLIFIER_GAIN_MIN, range is [0, 8] mapping to [0dB, 24dB], step is 3dB uint8 reserved1 : 3; // [7:4], default = 0 uint8 adcInputAmplifierGainLeft : 4; // [3:0], default = ADC_INPUT_AMPLIFIER_GAIN_MIN, range is [0, 8] mapping to [0dB, 24dB], step is 3dB };

3.2.14 [0x22] ADC配置

#define ADC_OUTPUT_NORMAL 0 #define ADC_OUTPUT_INVERT 1 #define ADC_INPUT_LINEIN 0 #define ADC_INPUT_LNA 1 #define MIC_INPUT_RIGHT_ADC 0 #define MIC_INPUT_LEFT_ADC 1 #define DC_FILTER_ENABLE 0 #define DC_FILTER_BYPASS 1 #define DC_FILTER_OFF 0 #define DC_FILTER_ON 1 struct { uint8 reserved0 : 3; // [15:13], default = 0 uint8 adcPolarity : 1; // [12], default = ADC_OUTPUT_NORMAL uint8 micInputVGAGain : 4; // [11:8], default = MIC_INPUT_GAIN_MIN, range is [0, 15] mapping to [0dB, 30dB], step is 2dB uint8 reserved1 : 4; // [7:4], default = 0 uint8 leftADCFunction : 1; // [3], default = ADC_INPUT_LINEIN uint8 micInputChannel : 1; // [2], default = MIC_INPUT_RIGHT_ADC uint8 dcFilterBypass : 1; // [1], default = DC_FILTER_BYPASS uint8 dcFileterPower : 1; // [0], default = DC_FILTER_OFF };

3.2.15 [0x23] 自动增益控制

#define AGC_TIME_0 0 // 44.1kHz(attack:11ms, decay:100ms) 8kHz(attack:61ms, decay:551ms) #define AGC_TIME_1 1 // 44.1kHz(attack:16ms, decay:100ms) 8kHz(attack:88.2ms, decay:551ms) #define AGC_TIME_2 2 // 44.1kHz(attack:11ms, decay:200ms) 8kHz(attack:61ms, decay:1102ms) #define AGC_TIME_3 3 // 44.1kHz(attack:16ms, decay:200ms) 8kHz(attack:88.2ms, decay:1102ms) #define AGC_TIME_4 4 // 44.1kHz(attack:21ms, decay:200ms) 8kHz(attack:116ms, decay:1102ms) #define AGC_TIME_5 5 // 44.1kHz(attack:11ms, decay:400ms) 8kHz(attack:61ms, decay:2205ms) #define AGC_TIME_6 6 // 44.1kHz(attack:16ms, decay:400ms) 8kHz(attack:88.2ms, decay:2205ms) #define AGC_TIME_7 7 // 44.1kHz(attack:21ms, decay:400ms) 8kHz(attack:116ms, decay:2205ms) #define AGC_LEVEL_NEG_5.5 0 // -5.5dBFS #define AGC_LEVEL_NEG_8 1 // -8dBFS #define AGC_LEVEL_NEG_11.5 2 // -11.5dBFS #define AGC_LEVEL_NEG_14 3 // -14dBFS #define AGC_OFF 0 #define AGC_ON 1 struct { uint8 reserved0 : 5; // [15:11], default = 0 uint8 agcTime : 3; // [10:8], default = AGC_TIME_0, 44.1kHz(attack:11ms, decay:100ms) 8kHz(attack:61ms, decay:551ms) uint8 reserved1 : 4; // [7:4], default = 0 uint8 agcLevel : 2; // [3:2], default = AGC_LEVEL_NEG_5.5 uint8 reserved2 : 1; // [1], default = 0 uint8 agcPower : 1; // [0], default = AGC_OFF };

3.2.16 [0x28] 抽取器状态

3.2.17 [0x7F] 恢复L3默认值

此命令为软件重置，不需要发送数据

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名词解释

• ADC - Analog to Digit Converter, 模数转换器
• DAC - Digit to Analog Converter, 数模转换器
• AVC - Automatic Volumn Control, 自动音量控制
• PLL - Phase Locked Loop, 锁相环
• PGA - Programmable Gain Amplifier, 可编程增益放大器
• LNA - Low Noise Amplifer, 低噪声放大器
• FSDAC - Filter-Stream Digital-to-Analog Converter, 滤波流数模转换器

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草稿

/** * 1. 输入: 启用ADC line in * 禁用ADC Mic * 启用I2S in * 2. 输出：启用DAC * 启用Headphone driver * 禁用I2S out * 3. 时钟：启用WSPLL * * Line in: ADC + PGA * * REG_CLOCK = { * EV: 000 * EN_ADC: 1 * EN_DEC: 1 // Decimator从ADC中把模拟信号抽取为数字信号，ADC要配合DEC使用 * EN_DAC: 1 // FSDAC * EN_INT: 1 // Interpolater * ADC_CLK: 1 // 1 for WSPLL, 0 for SYSCLK * DAC_CLK: 1 // 1 for WSPLL, 0 for SYSCLK * SYS_DIV: 0 // 0 for 256fs, 1 for 384fs, 2 for 512fs, 3 for 768fs * PLL: 2 // 0 for 6.25~12.5kHz, 1 for 12.5~25kHz, 2 for 25~50kHz, 3 for 50~100kHz * } * * REG_I2S = { * SFORI: 0 // 0 for I2S, 1 for LSB-16bits, 2 for LSB-18bits, 3 for LSB-20bits, 4 for MSB * SEL_SOURCE: 1 // 0 for decimator as output, 1 for digital mixer output as output * SIM: 0 // 0 for digital output interface as SLAVE, 1 for digital output interface as MASTER * SFORO: 0 // 0 for I2S, 1 for LSB-16bits, 2 for LSB-18bits, 3 for LSB-20bits, 4 for LSB-24bits, 5 for MSB * } * * REG_PWR = { * PON_PLL: 1 // 0 for WSPLL off, 1 for WSPLL on * PON_HP: 1 // 0 for Headphone off, 1 for Headphone on * PON_DAC: 1 // 0 for DAC off, 1 for DAC on * PON_BIAS: 1 // 0 for ADC/AVC/FSDAC bias circuits off, 1 for ADC/AVC/FSDAC bias circuits on * EN_AVC: 0 // 0 for mix in line put through digital mixer to ouput, 1 for enable mixing-in ADC line input(via AVC unit) to the line output directly * PON_AVC: 0 // 0 for analog mixer off, 1 for analog mixer on * PON_LNA: 0 // 0 for LNA/SDC off, 1 for LNA/SDC on * PON_PGAL: 1 // 0 for PGA left off, 1 for PGA left on * PON_PGAR: 1 // 0 for PGA right off, 1 for PGA right on * PON_ADCL: 1 // 0 for ADC left off, 1 for ADC left on * PON_ADCR: 1 // 0 for ADC right off, 1 for ADC right on * * PON_HP and PON_DAC should be power on later for PLOP prevention * } * * REG_AMIX = { // The analog mixer has been power-off * AVCL: 0x3F // 0 for max, 2b for min, 3f for mute * AVCR: 0x3F // 0 for max, 2b for min, 3f for mute * } * * REG_MASTER_VOL = { * MVCR: 0x20 // 0 for max, f8 for min, fc for mute * MVCL: 0x20 // 0 for max, f8 for min, fc for mute * } * * REG_MIXER_VOL = { * MVC_ANALOG: 0x00 // 0 for max, e0 for min, fc for mute, channel 2 is decomator * MVC_DIGITAL: 0x00 // 0 for max, e0 for min, fc for mute, channel 1 is digital input * } * * REG_EQ = {} * * REG_MUTE = { * MT_MASTER: 1 // 0 for unmute, 1 for mute * MT_DIGITAL: 1 // 0 for unmute, 1 for mute * DE_DIGITAL: 0 // 0 for off, 1 for 32kHz de-emphasis, 2 for 44.1kHz de-emphasis, 3 for 48kHz de-emphasis, 4 for 96kHz de-emphasis, disable it cause we have no emphasis process * MT_ANALOG: 1 // 0 for unmute, 1 for mute * DE_ANALOG: 0 // 0 for off, 1 for 32kHz de-emphasis, 2 for 44.1kHz de-emphasis, 3 for 48kHz de-emphasis, 4 for 96kHz de-emphasis, disable it cause we have no emphasis process * * Unmute after starting * } * * REG_MIXER = { * DAC_POL_INV: 0 // 0 for disable, 1 for enable * SEL_NS: 1 // 0 for 3rd-order noise shaper(preferred at 8~32kHz), 1 for 5th-order noise shaper(preferred at 32~100kHz) * MIX_POS: 0 // if MIX is 0 + MIX_POS is 0, mixing will be disabled * MIX: 1 // 0 for disable mixer, 1 for enable mixer * * MIX = 1, MIX_POS = 0, mixing will be executed before EQ processing * } */