寮傛FIFO鐨刅erilog瀹炵幇瀹炰緥鍒嗘瀽

2020-02-28 18:25发布

鏈笘鏈€鍚庣敱 wmsk 浜?2013-1-22 11:36 缂栬緫

//----------------------STYLE #1--------------------------module fifo1(rdata, wfull, rempty, wdata, winc, wclk, wrst_n,rinc, rclk, rrst_n);parameter DSIZE = 8;parameter ASIZE = 4;output [DSIZE-1:0] rdata;output wfull;output rempty;input [DSIZE-1:0] wdata;input winc, wclk, wrst_n;input rinc, rclk, rrst_n;reg wfull,rempty;reg [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr, wq1_rptr,rq1_wptr;reg [ASIZE:0] rbin, wbin;reg [DSIZE-1:0] mem[0 : (1<<ASIZE)-1];wire [ASIZE-1:0] waddr, raddr;wire [ASIZE:0] rgraynext, rbinnext,wgraynext,wbinnext;wire rempty_val,wfull_val;//-----------------鍙屽彛RAM瀛樺偍鍣?-------------------assign rdata=mem[raddr];always@(posedge wclk)if (winc && !wfull) mem[waddr] <= wdata;//-------------鍚屾rptr 鎸囬拡-------------------------always @(posedge wclk or negedge wrst_n)if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};//-------------鍚屾wptr鎸囬拡---------------------------always @(posedge rclk or negedge rrst_n)if (!rrst_n) {rq2_wptr,rq1_wptr} <= 0;else {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};//-------------rempty浜х敓涓巖addr浜х敓-------------------//-------------------// GRAYSTYLE2 pointer//-------------------always @(posedge rclk or negedge rrst_n)beginif (!rrst_n) {rbin, rptr} <= 0;else {rbin, rptr} <= {rbinnext, rgraynext};end// Memory read-address pointer (okay to use binary to address memory)assign raddr = rbin[ASIZE-1:0];assign rbinnext = rbin + (rinc & ~rempty);assign rgraynext = (rbinnext>>1) ^ rbinnext;//---------------------------------------------------------------// FIFO empty when the next rptr == synchronized wptr or on reset//---------------------------------------------------------------assign rempty_val = (rgraynext == rq2_wptr);always @(posedge rclk or negedge rrst_n)beginif (!rrst_n) rempty <= 1'b1;else rempty <= rempty_val;end//---------------wfull浜х敓涓巜addr浜х敓------------------------------// GRAYSTYLE2 pointeralways @(posedge wclk or negedge wrst_n)if (!wrst_n) {wbin, wptr} <= 0;else {wbin, wptr} <= {wbinnext, wgraynext};// Memory write-address pointer (okay to use binary to address memory)assign waddr = wbin[ASIZE-1:0];assign wbinnext = wbin + (winc & ~wfull);assign wgraynext = (wbinnext>>1) ^ wbinnext;//------------------------------------------------------------------// Simplified version of the three necessary full-tests:// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));//------------------------------------------------------------------assign wfull_val = (wgraynext=={~wq2_rptr[ASIZE:ASIZE-1],wq2_rptr[ASIZE-2:0]});always @(posedge wclk or negedge wrst_n)if (!wrst_n) wfull <= 1'b0;else wfull <= wfull_val;endmodule
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wmsk
1楼-- · 2020-02-28 21:14
鏈笘鏈€鍚庣敱 wmsk 浜?2013-1-22 11:37 缂栬緫

//---------------------STYLE #2-------------------------

module fifo2 (rdata, wfull, rempty, wdata,

winc, wclk, wrst_n, rinc, rclk, rrst_n);

parameter DSIZE = 8;

parameter ASIZE = 4;

output [DSIZE-1:0] rdata;

output wfull;

output rempty;

input [DSIZE-1:0] wdata;

input winc, wclk, wrst_n;

input rinc, rclk, rrst_n;

wire [ASIZE-1:0] wptr, rptr;

wire [ASIZE-1:0] waddr, raddr;


async_cmp #(ASIZE) async_cmp(.aempty_n(aempty_n),

.afull_n(afull_n),

.wptr(wptr), .rptr(rptr),

.wrst_n(wrst_n));


fifomem2 #(DSIZE, ASIZE) fifomem2(.rdata(rdata),

.wdata(wdata),

.waddr(wptr),

.raddr(rptr),

.wclken(winc),

.wclk(wclk));


rptr_empty2 #(ASIZE) rptr_empty2(.rempty(rempty),

.rptr(rptr),

.aempty_n(aempty_n),

.rinc(rinc),

.rclk(rclk),

.rrst_n(rrst_n));


wptr_full2 #(ASIZE) wptr_full2(.wfull(wfull),

.wptr(wptr),

.afull_n(afull_n),

.winc(winc),

.wclk(wclk),

.wrst_n(wrst_n));

endmodule

module fifomem2 (rdata, wdata, waddr, raddr, wclken, wclk);

parameter DATASIZE = 8; // Memory data word width

parameter ADDRSIZE = 4; // Number of memory address bits

parameter DEPTH = 1<<ADDRSIZE; // DEPTH = 2**ADDRSIZE

output [DATASIZE-1:0] rdata;

input [DATASIZE-1:0] wdata;

input [ADDRSIZE-1:0] waddr, raddr;

input wclken, wclk;

`ifdef VENDORRAM

// instantiation of a vendor's dual-port RAM

VENDOR_RAM MEM (.dout(rdata), .din(wdata),

.waddr(waddr), .raddr(raddr),

.wclken(wclken), .clk(wclk));

`else

reg [DATASIZE-1:0] MEM [0: DEPTH-1];

assign rdata = MEM[raddr];

always @(posedge wclk)

if (wclken) MEM[waddr] <= wdata;

`endif

endmodule

module async_cmp (aempty_n, afull_n, wptr, rptr, wrst_n);

parameter ADDRSIZE = 4;

parameter N = ADDRSIZE-1;

output aempty_n, afull_n;

input [N:0] wptr, rptr;

input wrst_n;

reg direction;

wire high = 1'b1;

wire dirset_n = ~( (wptr[N]^rptr[N-1]) & ~(wptr[N-1]^rptr[N]));

wire dirclr_n = ~((~(wptr[N]^rptr[N-1]) & (wptr[N-1]^rptr[N])) |

~wrst_n);

always @(posedge high or negedge dirset_n or negedge dirclr_n)

if (!dirclr_n) direction <= 1'b0;

else if (!dirset_n) direction <= 1'b1;

else direction <= high;

//always @(negedge dirset_n or negedge dirclr_n)

//if (!dirclr_n) direction <= 1'b0;

//else direction <= 1'b1;

assign aempty_n = ~((wptr == rptr) && !direction);

assign afull_n = ~((wptr == rptr) && direction);

endmodule

module rptr_empty2 (rempty, rptr, aempty_n, rinc, rclk, rrst_n);

parameter ADDRSIZE = 4;

output rempty;

output [ADDRSIZE-1:0] rptr;

input aempty_n;

input rinc, rclk, rrst_n;

reg [ADDRSIZE-1:0] rptr, rbin;

reg rempty, rempty2;

wire [ADDRSIZE-1:0] rgnext, rbnext;

//---------------------------------------------------------------

// GRAYSTYLE2 pointer

//---------------------------------------------------------------

always @(posedge rclk or negedge rrst_n)

if (!rrst_n) begin

rbin <= 0;

rptr <= 0;

end

else begin

rbin <= rbnext;

rptr <= rgnext;

end

//---------------------------------------------------------------

// increment the binary count if not empty

//---------------------------------------------------------------

assign rbnext = !rempty ? rbin + rinc : rbin;

assign rgnext = (rbnext>>1) ^ rbnext; // binary-to-gray conversion

always @(posedge rclk or negedge aempty_n)

if (!aempty_n) {rempty,rempty2} <= 2'b11;

else {rempty,rempty2} <= {rempty2,~aempty_n};

endmodule

module wptr_full2 (wfull, wptr, afull_n, winc, wclk, wrst_n);

parameter ADDRSIZE = 4;

output wfull;

output [ADDRSIZE-1:0] wptr;

input afull_n;

input winc, wclk, wrst_n;

reg [ADDRSIZE-1:0] wptr, wbin;

reg wfull, wfull2;

wire [ADDRSIZE-1:0] wgnext, wbnext;

//---------------------------------------------------------------

// GRAYSTYLE2 pointer

//---------------------------------------------------------------

always @(posedge wclk or negedge wrst_n)

if (!wrst_n) begin

wbin <= 0;

wptr <= 0;

end

else begin

wbin <= wbnext;

wptr <= wgnext;

end

//---------------------------------------------------------------

// increment the binary count if not full

//---------------------------------------------------------------

assign wbnext = !wfull ? wbin + winc : wbin;

assign wgnext = (wbnext>>1) ^ wbnext; // binary-to-gray conversion

always @(posedge wclk or negedge wrst_n or negedge afull_n)

if (!wrst_n ) {wfull,wfull2} <= 2'b00;

else if (!afull_n) {wfull,wfull2} <= 2'b11;

else {wfull,wfull2} <= {wfull2,~afull_n};

endmodule


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jlass
2楼-- · 2020-02-29 00:45
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GoldSunMonkey
3楼-- · 2020-02-29 02:54
jlass 鍙戣〃浜?2013-1-22 11:51
浠庣粨鏋勪笂璁诧紝妯″潡鍖栬偗瀹氭洿濂姐€?/blockquote>
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wmsk
4楼-- · 2020-02-29 07:00
 精彩回答 2  元偷偷看……
GoldSunMonkey
5楼-- · 2020-02-29 09:39
wmsk 鍙戣〃浜?2013-1-23 22:21
璋㈣阿澶у鐨勬敮鎸佸晩

涓嶈澶姘斿晩
vincentyeh
6楼-- · 2020-02-29 10:24
AL460 Full HD FIFO DRAM 鐨勫熀鏈粨鏋凢IFO(First in First out) 绗﹀悎楂橀€熷奖鍍忓厛杩涘厛鍑虹殑缁撴瀯锛屽挨鍏堕€傜敤浜庢暟鐮佸奖鍍忚祫鏂欑殑鏆傚瓨鍣ㄤ娇鐢ㄣ€?br /> 涓€锛庣嫭绔嬬殑鍐欏叆/ 杈撳嚭绋嬪簭锛岃緝浣庣殑杈撳叆clock rate,鍙湁鏁堝湴涓鸿吹鍙哥畝鍖栧紑鍙戞垚鏈互鍙婃椂闂淬€?br /> 浜岋紟鏀彺褰卞儚/鍥惧儚鏁颁綅璧勬枡VGA鍒?080p,鍐呴儴鏋舵瀯涓?Mx 16bit璁板繂浣撴灦鏋勶紝鏈€楂橀€熷害鍙揪鍒?50MHz,鍙弧瓒?080p鐨勮璁¢渶姹傘€?br /> 涓夛紟鍏锋湁杈撳叆/杈撳嚭鏅鸿兘鎺у埗(enable control) , 鍙仛鍙屽€嶈蹇嗕綋(double buffer)鎺у埗锛屽湪frame 鍥炬鎺у埗缂栫▼涓婂挨鍏舵柟渚裤€?br />

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