TI

简单的计数程序输出结果总是不对，求大牛帮忙

2019-11-21 13:46发布

站内问答 / FPGA
9106 1 1030
<p>我的程序是自己编写第一个通讯端口，其中FPGAtoAD_state是数据输出端口，PGAtoAD_clk_in是时钟输入端口，FPGAtoAD_data是数据输入端口，位宽为8位，FPGAtoAD_clk_out是时钟输出端口程序的主要流程如下：一开始是向上位机传一次数据，首先FPGAtoAD_clk_out拉低，等待上位机的PGAtoAD_clk_in时钟信号拉低表示上位机准备就绪，然后FPGAtoAD_clk_out置高，等待上位机的PGAtoAD_clk_in时钟信号置高就表示上位机读取成功，然后开始上位机向FPGA开始传输66次数据，每次传输以上位机的PGAtoAD_clk_in时钟信号拉低，然后FPGAtoAD_clk_out拉低表示准备好接受数据，之后PGAtoAD_clk_in时钟信号置高，等FPGAtoAD_clk_out也置高表示一次数据传输完成，反复66次，计数结果为参数n<br>现在的问题就是FPGA计数有问题，用示波器看了，要不是到64次就不响应，要不就是中间丢两个数据，又或者是传输66次之后还在等待传输，有时偶尔能正常传输几次，但很快就又会漏数据。<br>求各位大牛帮我看看程序，看问题在哪<br>不胜感谢，小弟这里只有168个积分，尽数奉上<br>系统时钟频率为50 MHz<br>具体程序如下</p><pre style="max-width: 100%;"><code class="plaintext"><code class="cpp hljs" codemark="1"><span class="hljs-comment">/******************************************* FPGAtoAD *******************************************/</span> reg [<span class="hljs-number">1</span>:<span class="hljs-number">0</span>] FPGAtoAD_rw; reg [<span class="hljs-number">7</span>:<span class="hljs-number">0</span>] n; reg [<span class="hljs-number">7</span>:<span class="hljs-number">0</span>] x; parameter outime=<span class="hljs-number">50</span>_000_000; <span class="hljs-comment">//reg ADCdata </span> <span class="hljs-comment">/* // //FPGA_R // */</span> <span class="hljs-comment">// wire FPGAtoAD_clk_out_w;</span> <span class="hljs-comment">// reg FPGAtoAD_clk_out_r;</span> <span class="hljs-comment">// </span> <span class="hljs-comment">// assign FPGAtoAD_clk_out= FPGAtoAD_rw ? FPGAtoAD_clk_out_r:FPGAtoAD_clk_out_w;</span> reg [<span class="hljs-number">3</span>:<span class="hljs-number">0</span>] FPGA_r_state; parameter R_idel = <span class="hljs-number">4</span><span class="hljs-string">'b0000; parameter R_start = 4'</span>b0001; parameter R_GetD = <span class="hljs-number">4</span><span class="hljs-string">'b0011; parameter R_WaitD = 4'</span>b0010; parameter R_over = <span class="hljs-number">4</span><span class="hljs-string">'b0110; parameter R_Busy = 4'</span>b1000; <span class="hljs-comment">/* // //FPGA_W // */</span> reg [<span class="hljs-number">3</span>:<span class="hljs-number">0</span>] FPGA_w_state; parameter W_idel = <span class="hljs-number">4</span><span class="hljs-string">'b0000; parameter w_start = 4'</span>b0001; parameter w_adbusy= <span class="hljs-number">4</span><span class="hljs-string">'b1000; parameter w_sclk_L= 4'</span>b0011; parameter w_buftim= <span class="hljs-number">4</span><span class="hljs-string">'b0010; parameter w_sdata = 4'</span>b0110; parameter w_sover = <span class="hljs-number">4</span><span class="hljs-string">'b0111; /* // // // */ reg [7:0] inset_time; reg [7:0] sent_time; always @ (posedge sys_clk or negedge sys_rst) IF(!sys_rst) begin FPGAtoAD_rw &lt;= 2'</span>b00; inset_time&lt;=<span class="hljs-number">8</span><span class="hljs-string">'d0; sent_time&lt;=8'</span>d0; <span class="hljs-function">end <span class="hljs-keyword">else</span> <span class="hljs-title">if</span><span class="hljs-params">(FPGAtoAD_rw == <span class="hljs-number">2</span><span class="hljs-string">'b11) begin if(inset_time&gt;=8'</span>d100)</span> begin FPGAtoAD_rw &lt;</span>= <span class="hljs-number">2</span><span class="hljs-string">'b00; inset_time&lt;=8'</span>d0; end <span class="hljs-keyword">else</span> inset_time&lt;=inset_time+<span class="hljs-number">1</span><span class="hljs-string">'b1; end else if((FPGA_r_state == R_over)&amp;(FPGAtoAD_rw == 2'</span>b10)) begin FPGAtoAD_rw &lt;= <span class="hljs-number">2</span><span class="hljs-string">'b11; sent_time&lt;=sent_time+1'</span>b1; <span class="hljs-function">end <span class="hljs-keyword">else</span> <span class="hljs-title">if</span><span class="hljs-params">((FPGA_w_state == w_sover)</span>&amp;<span class="hljs-params">(FPGAtoAD_rw == <span class="hljs-number">2</span><span class="hljs-string">'b01)) FPGAtoAD_rw &lt;= 2'</span>b10; <span class="hljs-keyword">else</span> <span class="hljs-keyword">if</span>(FPGAtoAD_rw == <span class="hljs-number">2</span><span class="hljs-string">'b00) FPGAtoAD_rw &lt;= 2'</span>b01; <span class="hljs-keyword">else</span> ; reg [<span class="hljs-number">7</span>:<span class="hljs-number">0</span>] pre_state; reg [<span class="hljs-number">25</span>:<span class="hljs-number">0</span>] to_cnt; <span class="hljs-comment">//timeout</span> wire [<span class="hljs-number">7</span>:<span class="hljs-number">0</span>] n_add; reg [<span class="hljs-number">7</span>:<span class="hljs-number">0</span>] n_buf; assign n_add=n+<span class="hljs-number">1</span><span class="hljs-string">'b1; always @ (posedge sys_clk or negedge sys_rst) if(!sys_rst) begin FPGA_r_state &lt;= R_idel; FPGA_w_state &lt;= W_idel; //FPGAtoAD_clk_out &lt;= 1'</span>b1; n &lt;= <span class="hljs-number">8</span><span class="hljs-string">'h0; to_cnt &lt;= 26'</span>d0; pre_state &lt;= <span class="hljs-number">8</span><span class="hljs-string">'d0; FPGAtoAD_clk_out &lt;= 1'</span>b1; FPGAtoAD_state &lt;= <span class="hljs-number">5</span><span class="hljs-string">'d0; n_buf &lt;= 8'</span>h0; <span class="hljs-keyword">for</span>(x=<span class="hljs-number">8</span><span class="hljs-string">'d0;x&lt;8'</span>d66;x=x+<span class="hljs-number">1</span><span class="hljs-string">'b1) ADCdata[x] &lt;= 8'</span>d0; end <span class="hljs-keyword">else</span> <span class="hljs-keyword">if</span>(FPGAtoAD_rw == <span class="hljs-number">2</span><span class="hljs-string">'b10) begin case(FPGA_r_state) R_idel: if(!FPGAtoAD_clk_in) begin n &lt;= 8'</span>h0; FPGA_r_state &lt;= R_start; to_cnt &lt;= <span class="hljs-number">26</span><span class="hljs-string">'d0; FPGAtoAD_clk_out &lt;= 1'</span>b1; end <span class="hljs-keyword">else</span> FPGA_r_state &lt;= R_idel; R_start: <span class="hljs-keyword">if</span>(FPGAtoAD_clk_in)</span> begin FPGAtoAD_clk_out &lt;</span>= <span class="hljs-number">1</span><span class="hljs-string">'b0; FPGA_r_state &lt;= R_GetD; to_cnt &lt;= 26'</span>d0; <span class="hljs-function">end <span class="hljs-keyword">else</span> <span class="hljs-title">if</span><span class="hljs-params">(to_cnt&lt;=<span class="hljs-number">26</span><span class="hljs-string">'d1000) begin FPGAtoAD_clk_out &lt;= 1'</span>b0; FPGA_r_state &lt;= R_start; to_cnt&lt;= to_cnt +<span class="hljs-number">1</span><span class="hljs-string">'b1; end else begin to_cnt &lt;= 26'</span>d0; FPGA_r_state &lt;= R_Busy; pre_state &lt;=R_start; end R_GetD: begin n_buf &lt;= n_add; FPGAtoAD_clk_out &lt;= <span class="hljs-number">1</span><span class="hljs-string">'b1; ADCdata[n] &lt;= FPGAtoAD_data; if(n == 8'</span>h41)</span> begin n &lt;</span>= <span class="hljs-number">8</span><span class="hljs-string">'h0; FPGA_r_state &lt;= R_over; end else begin FPGA_r_state &lt;= R_WaitD; end end R_WaitD: if(!FPGAtoAD_clk_in) begin n&lt;=n_buf; FPGA_r_state &lt;= R_start; to_cnt &lt;= 26'</span>d0; <span class="hljs-function">end <span class="hljs-keyword">else</span> <span class="hljs-title">if</span><span class="hljs-params">(to_cnt&lt;=<span class="hljs-number">26</span><span class="hljs-string">'d1000) begin to_cnt&lt;= to_cnt +1'</span>b1; FPGA_r_state &lt;= R_WaitD; end <span class="hljs-keyword">else</span> begin to_cnt &lt;= <span class="hljs-number">26</span><span class="hljs-string">'d0; FPGA_r_state &lt;= R_Busy; pre_state &lt;=R_WaitD; end R_Busy: FPGAtoAD_clk_out &lt;= 1'</span>b1;<span class="hljs-comment">//FPGA_r_state &lt;= R_over;</span> R_over: begin n &lt;= <span class="hljs-number">8</span><span class="hljs-string">'h0; to_cnt &lt;= 26'</span>d0; FPGAtoAD_clk_out &lt;= <span class="hljs-number">1</span><span class="hljs-string">'b1; end default: FPGA_r_state &lt;= R_idel; endcase end else if(FPGAtoAD_rw == 2'</span>b01)</span> begin <span class="hljs-title">case</span><span class="hljs-params">(FPGA_w_state)</span> W_idel: begin FPGAtoAD_clk_out &lt;</span>= <span class="hljs-number">1</span><span class="hljs-string">'b1; FPGAtoAD_state &lt;= 5'</span>d0; FPGA_w_state &lt;= w_start; end w_start: <span class="hljs-comment">//确认AD模块空闲</span> begin FPGAtoAD_clk_out &lt;= <span class="hljs-number">1</span><span class="hljs-string">'b1; FPGAtoAD_state &lt;= 5'</span>d0; <span class="hljs-keyword">if</span>(to_cnt&lt; <span class="hljs-number">26</span><span class="hljs-string">'d1000) //ensure AD MOD free begin if(!FPGAtoAD_clk_in) begin FPGA_w_state &lt;= w_adbusy; pre_state &lt;=w_start; to_cnt &lt;= 26'</span>d0; end <span class="hljs-keyword">else</span> to_cnt&lt;=to_cnt+<span class="hljs-number">1</span><span class="hljs-string">'b1; end else begin FPGA_w_state &lt;= w_sclk_L; to_cnt &lt;= 26'</span>d0; end end w_adbusy: FPGA_w_state &lt;= W_idel; w_sclk_L: <span class="hljs-comment">//确认AD模块空闲后拉低FPGA写时钟</span> begin <span class="hljs-comment">//并等待AD模块时钟拉低</span> FPGAtoAD_clk_out &lt;= <span class="hljs-number">1</span><span class="hljs-string">'b0; FPGAtoAD_state &lt;= FPGAtoAD_commd; if(!FPGAtoAD_clk_in) //AD模块时钟拉低后等待数据读取 begin //FPGA_w_state &lt;= w_sdata; to_cnt &lt;= 26'</span>d0; FPGA_w_state &lt;= w_buftim; <span class="hljs-comment">//</span> <span class="hljs-function">end <span class="hljs-keyword">else</span> <span class="hljs-title">if</span><span class="hljs-params">(to_cnt<outime)< span=""> begin FPGA_w_state &lt;</outime)<></span>= w_sclk_L; to_cnt &lt;= to_cnt+<span class="hljs-number">1</span><span class="hljs-string">'b1; end else begin FPGA_w_state &lt;= w_adbusy; pre_state &lt;=w_sclk_L; to_cnt &lt;= 26'</span>d0; end end w_buftim: begin FPGAtoAD_clk_out &lt;= <span class="hljs-number">1</span><span class="hljs-string">'b0; FPGAtoAD_state &lt;= FPGAtoAD_commd; FPGA_w_state &lt;= w_sdata; end w_sdata: begin FPGAtoAD_clk_out &lt;= 1'</span>b1; FPGAtoAD_state &lt;= FPGAtoAD_commd; <span class="hljs-keyword">if</span>(FPGAtoAD_clk_in) begin FPGA_w_state &lt;= w_sover; to_cnt &lt;= <span class="hljs-number">26</span><span class="hljs-string">'d0; end else if(to_cnt&lt;26'</span>d1010) begin FPGA_w_state &lt;= w_sdata; to_cnt &lt;= to_cnt+<span class="hljs-number">1</span><span class="hljs-string">'b1; end else begin FPGA_w_state &lt;= w_adbusy; pre_state &lt;=w_sdata; to_cnt &lt;= 26'</span>d0; end end w_sover: begin to_cnt &lt;= <span class="hljs-number">26</span><span class="hljs-string">'d0; FPGAtoAD_clk_out &lt;= 1'</span>b1; FPGAtoAD_state &lt;= <span class="hljs-number">5</span><span class="hljs-string">'d0; n &lt;= 8'</span>h0; end <span class="hljs-comment">//FPGA_w_state &lt;= W_idel;</span> <span class="hljs-keyword">default</span>: begin FPGAtoAD_clk_out &lt;= <span class="hljs-number">1</span><span class="hljs-string">'b1; FPGAtoAD_state &lt;= 5'</span>d0; FPGA_w_state &lt;= W_idel; end endcase end <span class="hljs-keyword">else</span> begin FPGA_r_state &lt;= R_idel; FPGA_w_state &lt;= W_idel; n &lt;= <span class="hljs-number">8</span><span class="hljs-string">'h0; to_cnt &lt;= 26'</span>d0; FPGAtoAD_clk_out &lt;= <span class="hljs-number">1</span><span class="hljs-string">'b1; FPGAtoAD_state &lt;= 5'</span>d0; end</span></code></code></pre><p><em>复制代码</em>补充说明一下：<br>计数的是n<br>其实原来的计数我是简单的通过n&lt;= n+1'b1;<br>这个语句来实现的，但是计数有问题我才改成现在这样的<br>原来的程序没有<br>wire [7:0] n_add;<br>reg [7:0] n_buf;<br>这两个参数，但是计数还是有问题<br>除此之外，我写的部分程序利用计数来实现时序控制，有时也是会有时序抖动的问题，估计问题也是出在计数输出结果不对。<br>求大牛指点</p><p><br></p>
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星云云
1楼-- · 2019-11-21 13:51
程序没来得及仔细看，你可以试试先用modelsim仿真，仔细看下逻辑有没有问题。如果逻辑没出问题，那就应该是时序出现问题了，把那个assign语句改一下，这样写时钟不太好，IP核有一个选择时钟的，我忘了是哪个了，你可以找一下。

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