<p> 现在我在Vivado中做了一个基于axi总线测量频率的ip核，不知道在sdk中怎么读出频率计数值，</p><p>`timescale 1ns / 1ps</p><br><br> <pre style="max-width: 100%;"><code class="cpp hljs" codemark="1"><span class="hljs-comment">//////////////////////////////////////////////////////////////////////////////////</span> <span class="hljs-comment">// Company: </span> <span class="hljs-comment">// Engineer: </span> <span class="hljs-comment">// </span> <span class="hljs-comment">// Create Date: 2019/07/20 11:04:26</span> <span class="hljs-comment">// Design Name: </span> <span class="hljs-comment">// Module Name: meas_freq</span> <span class="hljs-comment">// Project Name: </span> <span class="hljs-comment">// Target Devices: </span> <span class="hljs-comment">// Tool Versions: </span> <span class="hljs-comment">// Description: </span> <span class="hljs-comment">// </span> <span class="hljs-comment">// Dependencies: </span> <span class="hljs-comment">// </span> <span class="hljs-comment">// Revision:</span> <span class="hljs-comment">// Revision 0.01 - File Created</span> <span class="hljs-comment">// Additional Comments:</span> <span class="hljs-comment">// </span> <span class="hljs-comment">//////////////////////////////////////////////////////////////////////////////////</span> <span class="hljs-function">module <span class="hljs-title">meas_freq</span><span class="hljs-params">( input clk_100M, <span class="hljs-comment">//100MHz系统时钟</span> input square , output wire [<span class="hljs-number">27</span>:<span class="hljs-number">0</span>] CNTCLK, <span class="hljs-comment">//闸门内系统时钟周期计数</span> output wire [<span class="hljs-number">27</span>:<span class="hljs-number">0</span>] CNTSQU <span class="hljs-comment">//闸门内待测方波时钟周期计数</span> )</span></span>; parameter GATE_TIME = <span class="hljs-number">28</span><span class="hljs-string">'d99_999_999;//实际闸门计数是99_999_999，仿真时设为10ms reg square_r0 = 1'</span>b0; reg square_r1 = <span class="hljs-number">1</span><span class="hljs-string">'b0; reg square_r2 = 1'</span>b0; reg square_r3 = <span class="hljs-number">1</span><span class="hljs-string">'b0; reg [27:0] cnt1 = 28'</span>d0; <span class="hljs-comment">//产生 1s 的闸门信号的计数器</span> reg gate = <span class="hljs-number">1</span><span class="hljs-string">'b0; //闸门信号 reg gatebuf = 1'</span>b0; <span class="hljs-comment">//与方波同步之后的闸门信号</span> reg gatebuf1 = <span class="hljs-number">1</span><span class="hljs-string">'b0;//同步闸门信号延时一拍 reg [27:0] cnt2 = 28'</span>d0; reg [<span class="hljs-number">27</span>:<span class="hljs-number">0</span>] cnt2_r = <span class="hljs-number">28</span><span class="hljs-string">'d0; reg [27:0] cnt3 = 28'</span>d0; reg [<span class="hljs-number">27</span>:<span class="hljs-number">0</span>] cnt3_r = <span class="hljs-number">28</span><span class="hljs-string">'d0; // reg [27:0] CNTCLK= 28'</span>d0; <span class="hljs-comment">// reg [27:0] CNTSQU= 28'd0;</span> wire square_pose,square_nege; wire gate_start,gate_end; <span class="hljs-comment">//使方波和100MHz时钟同步并捕捉待测方波的边沿</span> always @ (posedge clk_100M) begin square_r0 &lt;= square; square_r1 &lt;= square_r0;<span class="hljs-comment">//将外部输入的方波打两拍</span> square_r2 &lt;= square_r1; square_r3 &lt;= square_r2; end assign square_pose = square_r2 &amp; ~square_r3; assign square_nege = ~square_r2 &amp; square_r3; always @ (posedge clk_100M) <span class="hljs-function">begin <span class="hljs-title">IF</span><span class="hljs-params">(cnt1 == GATE_TIME)</span>begin cnt1 &lt;</span>= <span class="hljs-number">28</span><span class="hljs-string">'d0; gate &lt;= ~gate;//产生 1s 的闸门信号 end else begin cnt1 &lt;= cnt1 + 1'</span>b1; end end always @ (posedge clk_100M ) <span class="hljs-function">begin <span class="hljs-title">if</span><span class="hljs-params">(square_pose == <span class="hljs-number">1</span><span class="hljs-string">'b1)begin gatebuf &lt;= gate;//使闸门信号与待测方波同步，保证一个闸门包含整数个方波周期 end gatebuf1 &lt;= gatebuf;//将同步之后的闸门信号打一拍，用于捕捉闸门信号的边沿 end assign gate_start = gatebuf &amp; ~gatebuf1;//表示闸门开始时刻 assign gate_end = ~gatebuf &amp; gatebuf1;//闸门结束时刻 //计数系统时钟周期 always @ (posedge clk_100M) begin if(gate_start == 1'</span>b1)</span>begin cnt2 &lt;</span>= <span class="hljs-number">28</span><span class="hljs-string">'d1; end else if(gate_end == 1'</span>b1)begin cnt2_r &lt;= cnt2;<span class="hljs-comment">//将所得结果保存在cnt2_r中，并将计数器清零</span> cnt2 &lt;= <span class="hljs-number">28</span><span class="hljs-string">'d0; end else if(gatebuf1 == 1'</span>b1)begin<span class="hljs-comment">//在闸门内计数系统时钟周期</span> cnt2 &lt;= cnt2 + <span class="hljs-number">1</span><span class="hljs-string">'b1;end end //计数待测方波周期数 always @ (posedge clk_100M ) begin if(gate_start == 1'</span>b1)begin cnt3 &lt;= <span class="hljs-number">28</span><span class="hljs-string">'d0; end else if(gate_end == 1'</span>b1)begin cnt3_r &lt;= cnt3;<span class="hljs-comment">//将所得结果保存在cnt3_r中，并将计数器清零</span> cnt3 &lt;= <span class="hljs-number">28</span><span class="hljs-string">'d0; end else if(gatebuf1 == 1'</span>b1 &amp;&amp; square_nege == <span class="hljs-number">1</span><span class="hljs-string">'b1)begin//在闸门内计数待测方波周期数(数闸门内方波的下降沿） cnt3 &lt;= cnt3 + 1'</span>b1; end end assign CNTCLK = cnt2_r; assign CNTSQU = cnt3_r; endmodule </code></pre><p><br></p>