求dac8668的verilog驱动代码，最好是用zynq—7000平台可以用的

2019-11-21 13:42发布

我需要同时驱动两路da  因为这个da8568上有两个模拟输出A,B 希望大神帮我解决    球球你们   技术手册已上传    另外  我自己拙劣代码   也给大神们看看 <pre style="max-width: 100%;"><code class="cpp hljs" codemark="1">`timescale 1ns / 1ps module da( input clk,//125M的时钟！！！ input rst_n, output sclk,//为50M 所以周期20ns output cs_n,////输出通道就是那个sync output reg clr_n,//接高电平这样处理 output reg load_n,///ci此程序定义的那个接地同步不需要管 output din, //input [15:0] reg1, //input [15:0] reg2, output reg LED ); wire clk1; wire [15:0] reg1,reg2; //四个变量用了一个 //parameter CMD_SOFT_RST = 32'h1FFF_FFFF;//0001 11XX XXXX XXXX XXXX XXXX XXXX XXXX //parameter CMD_POWER_ON = 32'h090A0000; parameter CMD_WRITE_INPUT_REG = 32'h00000000; //parameter CMD_LOAD = 32'h060000FF;//32'h060000FF0000 0110 0000000000 涓嶅 鏀逛笅; 0000 0110 0000 0000 0000 0000 1111 1111 wire [15:0]DA1buff; wire [15:0]DA2buff; reg [31:0]PSbuff; reg [12:0]dacnt; //max=4095 reg xdaccsf; wire xdaccsb; wire we1,we2; clk_wiz_0 q ( // clock out ports .clk_out1(sclk), .clk_out2(clk1), // output clk_out1 // Status and control signals .reset(rst_n), // input reset // Clock in ports .clk_in1( clk)); wave_gen a( .clk1(clk1), .rst_n(rst_n), .reg1(reg1), .reg2(reg2) ); // DAC8568 是32位寄存器，写一次寄存器需要32个sclk assign we1 = (dacnt == 12'd1) ? 1'b1 : 1'b0; //we1 cnt 1 + 32 = 33 assign we2 = (dacnt == 12'd38) ? 1'b1 : 1'b0; //we2 cnt 38 + 32 = 70 assign xdaccsb = (dacnt > 12'd0 && dacnt < 12'd33) ? 1'b0 : //片选? 给100ns转换时间 (dacnt > 12'd38 && dacnt < 12'd71) ? 1'b0 : 1; assign DA1buff = reg1; //12'h555;//12'hFFF - DA1 ; assign DA2buff = reg2; //12'hAAA;//12'hFFF - DA2 ; //assign sclk = clk; assign cs_n = xdaccsf; assign din = PSbuff[31]; //assign clr_n = 1'b1; always @(posedge sclk or negedge rst_n) begin IF (rst_n) begin xdaccsf <= 1'b1; led<=1'b0; end else begin xdaccsf <= xdaccsb; led<=1'b1; end end always @(posedge sclk or negedge rst_n) begin if (rst_n) begin clr_n=1'b1; load_n=1'b0; dacnt <= 12'd0; PSbuff <= 32'h00000000; end else if( dacnt==12'd72) // 澶嶄綅鍚庣涓?涓懆鏈熻繘琛屽垵濮嬪寲 daenable 浣胯兘 dacnt <= 12'd0; else begin clr_n=1'b1; load_n=1'b0; dacnt <= dacnt+1'd1; if (we1) PSbuff <= CMD_WRITE_INPUT_REG | 0<<20 | DA1buff << 4; //因为后四位没用无关的移动是因为地址在动 else if (we2) PSbuff <= CMD_WRITE_INPUT_REG | 1<<20 | DA2buff << 4; else PSbuff <= {PSbuff[30:0],1'bZ}; //默认高阻态 end end endmodule `timescale 1ns / 1ps module wave_gen( clk1, rst_n,reg1,reg2 ); parameter c=16'd655; input clk1, rst_n; output [15:0] reg1, reg2; reg [15:0] y=1'b1; reg [15:0] cnt =1'b1; reg [15:0] cnt1 =1'b0; reg[15:0] reg1,reg2; always @(posedge clk1 or negedge rst_n) begin if (rst_n) begin cnt1 <= 12'd0; cnt <= 12'd1; end else if(cnt1==12'd72) // 澶嶄綅鍚庣涓?涓懆鏈熻繘琛屽垵濮嬪寲 daenable 浣胯兘 begin cnt1 <= 12'd0; cnt<=cnt+1; y<=c*cnt; end else if (cnt==100) cnt<=1; else begin cnt1 <= cnt1+1'd1; reg1<=y; reg2<=y; end end // always @(posedge clk or negedge rst_n) begin // if(rst_n) // begin // cnt1<=12'd0; // end // else // begin // reg1<=y; // reg2<=y; // end; // end endmodule[/size]</code></pre> <dl class="tattl"> </dl>

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