电源

ARM Power On/Off Sequence and Power State

2019-07-14 03:47发布

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---- Power up and down sequences Ananke follows the following approach to taking cores in the cluster in and out of coherence. To bring an Ananke core into coherence after reset, no micro-architectural software steps are required.  To take an Ananke core out of coherence ready for core power down,the followingpower down steps must be performed: 1)   Save all architectural state. 2)   To disable or reroute interrupts away from this core, configure the GIC distributor. 3)   Set * bit to 1 to indicate to power controller that a power down is requested. 4)   Executea WFI instruction. All cache disabling, cache flushing (L1 and L2), and communication with the L3 memory system is performed in hardware after the WFI is executed, under the direction of the power controller. Note：Executing any WFI instruction when * bit is set automatically masks out (屏蔽)all interrupts and  wake-up events in the core. If executed when * bit is set the WFI never wakes up and the core needs to be  reset to restart. (重启) An Ananke cluster is taken out of coherence with interconnect automatically when it is powered down, and  no software sequence is required. Hardware under the direction of the power controller performs the level-3  cache flushing and communicates with the interconnect to disable snoop into the cluster.  All cores must be powered down as described previously before the cluster can be powered down. ---- Power state control All power state transitions are performed at the request of the power controller, using P-Channel to communicate with the Ananke processor. (所有Power状态的转换都由power controller发出请求，用P-channel和Ananke处理器进行通信) There is one P-Channel per core, plus one P-Channel for the cluster.  Ananke provides the current requirements on the PACTIVE signals, so that the power controller can make  decisions and request any change with PREQ and PSTATE.  The Ananke processor then perform any actions necessary to reach the requested power state, such as  gating clocks, flushing caches, or disabling coherency, before accepting the request. If the request is not valid, either because of an incorrect transition or because the status has changed  and so that state is no longer appropriate, then the request will be denied. (如果请求是无效的，或者因为不正确的状态转换或者状态已经改变所以状态不在合适。) The power mode of each core can be independent of other cores in the cluster（Cluster内每个core的power  mode都是独立的），however the cluster power mode is linked to the state of the cores. ---- Power states ---- On In this mode, the core is on and fully operational(全面运转/运作). The core can be initialized into this state,  or tied in this state if the P-Channel is unused. When a transition to the On state is completed, all caches are accessible and coherent without needing any configuration from software, other than the normal architectural steps to enable caches.  When the core domain P-Channel is initialized into the On state, either as a shortcut for entering that  state or as a tie-off for an unused P-Channel, it is an assumed transition from the Off mode.Therefore, it will include an invalidation of any cache RAM within the core domain. ---- Off In this mode, all core logic and RAMs are Off. The domain is inoperable(不能操作的) and all core state is lost. The core can be power-on reset in this state. The core P-Channel can be initialized into this state. An attempted debug access when the core domain is off returns an error response on the internal debug  interface indicating the core is not available. ---- Off (emulated) In this mode, all core domain logic and RAMs are kept on.However functional logic is reset to emulate a power off scenario while keeping core debug state and allowing debug access. All debug registers must retain their state and be accessible from the external debug interface. All other  functional interfaces behave as if the core were Off. ---- SIMD Dynamic Retention In this mode, the Advanced SIMD and floating-point logic is in retention (inoperable but with state retained) and the remainder of the core logic is operational. This means that if an Advanced SIMD and floating-point instruction is required to be executed while in this  mode, it is stalled until the core enters the On mode. When the Advanced SIMD and floating-point logic is in retention, the clock to the logic is automatically gated outside of the retained domain. ---- Core Dynamic Retention In this mode, all core logic and RAMs are in retention, the core domain is inoperable but with core state retained. When in dynamic retention, the clock to the core is automatically gated outside of the domain. The outputs of the domain must be isolated to prevent buffers without power from propagating unknown values to any operational parts of the system. Debug access is supported when the core domain is in dynamic retention, so the core appears as if were in a WFI or WFE state. When a debug access occurs, it is stalled and the On PACTIVE bit set high. when the domain is returned to On via the P-Channel, the access can proceed. If the debug access is the only cause of the wake-up the core does  not exit WFI. When the debug access is complete, the domain begins an entry delay period, assuming all other retention entry conditions remain valid. If all retention entry conditions are met during the entry delay period, then the  On PACTIVE bit is set low and a request to reenter dynamic retention is accepted. Note: If SIMD dynamic retention is implemented and enabled, then the core does not indicate on PACTIVE that it can enter core dynamic retention until it is already in SIMD dynamic retention.